NextFin News - India is opening access to its $13.4 billion semiconductor fund, offering chip-design firms reimbursement of up to 50% of eligible expenditure and extending capital subsidies to the companies that build the machines and materials a fabrication plant cannot run without. The move, drawn from the Semicon 2.0 package approved by the Union Cabinet in July, marks a deliberate pivot: after years of chasing headline fabrication projects, New Delhi is now funding the higher-margin design and equipment layers of the chip supply chain — the segments where the United States, Europe and East Asia still collect most of the profit.
The Deal: What the Fund Actually Pays For
The money comes from a fiscal outlay of ₹1,27,500 crore — roughly $13.4 billion — approved on 15 July 2026 by the cabinet chaired by Prime Minister Narendra Modi. It is the second phase of the Semicon India Programme, and it is structured around six pillars: chip design; machines and materials; more fabrication plants; strengthening assembly, testing, marking and packaging; research and development; and talent development.
On the design side, the Design Linked Incentive scheme reimburses up to 50% of eligible expenditure for integrated circuits, chipsets, systems-on-chips, systems and IP cores, capped at ₹15 crore per application. Successful products then earn a deployment-linked payment of 4% to 6% of net sales turnover over five years, capped at ₹30 crore, with minimum cumulative sales of ₹1 crore for startups and MSMEs and ₹5 crore for other domestic companies. The fiscal support runs for six years, and the ChipIN Centre operated by C-DAC gives approved firms remote access to a national grid of electronic design automation tools, an IP-core repository, multi-project-wafer prototyping and post-silicon validation. Under the new phase, Indian companies and firms owned by overseas citizens of India may also participate, and a deployment-linked incentive is available to all eligible companies to offset tape-out costs.
On the manufacturing side, the programme offers fiscal support of 40% of capital expenditure on a pari-passu basis for CMOS silicon fabs, and 35% for compound semiconductor, discrete and display fabs. Advanced packaging facilities qualify for 35% of capex, and other packaging for 25%, also on a pari-passu basis. Companies manufacturing the machines, materials, chemicals and gases that fabs consume are now explicitly in scope — the first time equipment and materials makers have sat at the centre of the incentive architecture rather than at its edge.
The Cabinet has approved Semicon 2.0 with an outlay of Rs. 1,27,500 crore, reaffirming our long-term commitment to making India a global centre for semiconductor design, manufacturing and innovation.
Prime Minister Narendra Modi said in a statement on 15 July. Electronics and IT Minister Ashwini Vaishnaw has said the mission will prioritise indigenous chip design, productisation, talent development and attracting ecosystem partners.
The policy is not starting from zero. The government says 105 startups are already developing chips, 24 projects are supported under the design scheme, 105 companies have received advanced chip-design tools and 23 tapeouts have been completed. Twelve semiconductor manufacturing projects have been approved, representing an investment pipeline of about ₹1.64 lakh crore, including one fabrication unit, two compound-semiconductor units and nine packaging units. Three companies — Micron, Kaynes Semicon and CG Power's CG Semi — have already commenced commercial production, and the first new fab is scheduled to be commissioned in 2028.
The budget architecture behind the headline number matters. For fiscal 2026-27, the Modified Programme for Development of Semiconductor and Display Manufacturing carries an outlay of ₹8,000 crore, with a further ₹1,000 crore provisioned for Semicon 2.0 operations. The ₹1,27,500 crore is the multi-year envelope from which those annual allocations are drawn — a distinction that explains why disbursement will ramp over several years rather than arrive as a single cheque.
Why Design First, When India Has No High-Volume Fab Yet
The sequencing is the point, not a contradiction. Semiconductor design accounts for up to 50% of value addition in the electronics value chain, and roughly a third of global semiconductor sales flow through the fabless segment. Design is also capital-light relative to a fabrication plant: a design team can reach tapeout on a multi-project wafer for a fraction of the billions a fab demands. For a country with a deep pool of chip-design engineers but no leading-edge foundry, funding design first is the cheapest way to build IP ownership, sticky revenue streams and a customer base that a future fab can serve.
The transmission mechanism runs design wins → IP ownership → recurring royalty and licensing revenue → proof of demand that justifies domestic fabrication. Once Indian-designed chips reach volume, the economics of building a local fab improve because the offtake risk falls. That is why the deployment-linked incentive — 4% to 6% of net sales for five years — matters as much as the upfront design reimbursement: it rewards products that actually sell, not prototypes that sit on a shelf.
This is a structural intervention, not a cyclical stimulus. A cyclical policy smooths a downturn and then withdraws; Semicon 2.0 changes the rules of the game for a decade or more. The six-year support window, the permanent design-infrastructure grid and the explicit equipment-and-materials pillar are regime-level commitments. But within that structural shift, near-term uptake is cyclical and execution-dependent: applications, approvals and tapeouts will arrive in lumps, not a smooth line.
The talent base is the quiet pillar that makes the design-first logic plausible. The government says 332 universities are now training students on complex chip design using the latest EDA tools, with around 70,000 students already trained. That is a large engineering funnel, though the relevant comparison is not the headcount but the retention rate: India has long exported its best chip designers to Silicon Valley, and the deployment-linked incentive is, in part, a wage subsidy designed to make domestic design work pay enough to keep them.
The Tata Electronics–ASML agreement of 16 May 2026 illustrates both the ambition and the timeline. ASML will supply advanced manufacturing technology and equipment for a 300mm wafer fab in Dholera, Gujarat, backed by an estimated $11 billion investment. ASML chief executive Christophe Fouquet said India's rapidly expanding semiconductor sector presents substantial long-term opportunities. Yet that fab is not due until 2028 — which is precisely why New Delhi is funding design and equipment today rather than waiting for silicon to flow.
The Equipment Gap Is the Harder Bet — and the Bigger Prize
The machines-and-materials pillar is the riskier half of the package, and the one with more upside. Semiconductor manufacturing equipment is dominated by a small group of Western and Japanese suppliers; the tools that etch, deposit and inspect nanometre-scale features are among the most complex machines ever built. India's precision-manufacturing base, however, is real, and state-level incentives in Gujarat, Uttar Pradesh and Karnataka can layer on top of the central support — advisory estimates put combined central and state support as high as 60% to 75% of project cost in favoured locations.
The second-order logic is what makes this worth attempting. If India can localize even a subset of fab equipment — chambers, robotics, gas-delivery systems, specialty chemicals — the capital cost of every future Indian fab falls, which makes the capex subsidy stretch further and improves the return case for the next wave of foundry investment. In other words, the equipment pillar is not a separate initiative; it is a lever on the economics of the entire fab programme. A fab subsidy that shrinks the fab's bill of equipment is worth more than its face value.
There is also a geopolitical channel. Export controls have made advanced chipmaking equipment a strategic chokepoint. A domestic equipment base does not remove that constraint at the leading edge, but it does reduce exposure in mature nodes, where India is more likely to compete first. Mature-node equipment is less restricted, more standardised and closer to India's current manufacturing capability — a realistic beachhead rather than a moonshot.
The Regional Race India Is Actually Running
India's reference points are not Taiwan or South Korea — those positions are occupied and defended by incumbents with decades of accumulated process knowledge. The realistic comparison is with China in the 2000s and Vietnam today: countries that entered the supply chain at the labour-intensive and mature-node end and climbed from there.
China's path is instructive because it shows both the ceiling and the floor. Beijing's subsidies built a large domestic design industry and a meaningful mature-node foundry base, but the most advanced equipment remained out of reach once export controls tightened. India's lesson is that design and mature-node equipment can be indigenized, while leading-edge tools will remain imported for the foreseeable future — which is exactly the boundary Semicon 2.0 draws. Vietnam's path is the nearer benchmark: it has moved quickly into packaging and assembly by offering speed, power reliability and administrative clarity rather than the deepest subsidy. That is the competition for the packaging tranche of the fund, and it is a race India wins on scale and domestic demand, not on subsidy depth alone.
The design track record gives some grounds for confidence. Through 2024, more than 32 startups and MSMEs had received benefits from the Design Linked Incentive scheme, with over ₹500 crore disbursed, producing innovations in automotive systems-on-chips, 5G modems and AI chipsets. That is a modest base by global standards, but it is a functioning one — and the new phase widens the funnel by allowing OCI-owned companies to participate and by subsidizing tape-outs for all eligible firms.
What the Market Has Priced In — and What It Has Not
Indian equities with semiconductor exposure — HCLTech, Tata Elxsi, CG Power, Vedanta, Kaynes Technology and Moschip among them — have re-rated over the past year on the fab announcements and the broader policy push. That repricing reflects the visible, capital-intensive part of the story: construction, packaging, and the promise of a fab economy. CG Power, for example, already reports semiconductor revenue as a separate segment; its CG Semi project has received approval for central government fiscal support of up to approximately ₹3,501 crore, and its semiconductor business generated around ₹503 crore of revenue in FY26 while reporting a segment loss of about ₹108 crore — a reminder that early-stage chip economics are rarely kind.
The design and equipment tranche announced now is less fully priced, for two reasons. First, the payouts are smaller and slower: a ₹15 crore design cap and a ₹30 crore deployment cap do not move a large-cap's earnings needle on their own. Second, the beneficiaries are earlier-stage and more numerous — startups and MSMEs rather than a handful of listed names — so the value accrues diffusely through the ecosystem before it concentrates in any single stock.
The second-order cross-market implication is currency. Indian design firms bill in dollars while their costs are largely rupee-denominated; a weaker rupee widens their margin on the same design win, while a stronger rupee compresses it. The deployment-linked incentive, paid as a percentage of sales, partially offsets that exposure but does not eliminate it. For equipment makers, the opposite dynamic applies: imported components raise costs when the rupee weakens, even as domestic fab demand rises.
The Case Against — and the Signal That Would Prove It
The strongest argument against this strategy is that India's semiconductor ambitions have a long record of announcement without delivery. Fabrication projects have slipped repeatedly, design talent emigrates to higher-paying markets, and the per-project caps are too small to attract global equipment leaders who can earn far more selling to established fabs in Taiwan, South Korea and Arizona. On this view, Semicon 2.0 is a well-funded continuation of a pattern: impressive outlays, modest outcomes.
The counter to that is that the policy has changed shape. The first phase was largely a greenfield fab chase; Semicon 2.0 leads with the segment where India already has a foothold — 105 startups in the design pipeline, 23 completed tapeouts, a functioning national EDA grid — and only then builds outward to equipment and mature-node manufacturing. That sequencing is more defensible than the old one. The ₹15 crore design cap is small for a large company but meaningful for an MSME; the deployment incentive rewards commercial success, which filters out subsidy-seekers.
Even so, the thesis needs a falsifying signal. If by the end of 2027 fewer than 30 design projects have been approved under Semicon 2.0, and no semiconductor-equipment manufacturer has broken ground on an Indian facility, the strategy should be judged as stalling rather than sequencing. That is a concrete threshold, not a vague call to "watch execution."
What Comes Next
In the short term, expect announcement flow and equity beta: design approvals, state-level memoranda of understanding, and volatility in the semiconductor-exposed index names around events such as the SEMICON India 2026 conference in New Delhi from 17 to 19 September 2026. In the medium term, the relevant metrics are tapeouts, design wins and deployment-linked payouts — the point at which subsidized designs become revenue. In the long term, the whole thesis rests on the first fab reaching volume in 2028 and on at least one domestic equipment supplier reaching qualified-vendor status.
The base case is that India deepens its design ecosystem and stands up a handful of equipment pilot lines, with fabrication arriving on schedule at the end of the decade. The upside case is a global equipment joint venture that localizes mature-node tools faster than expected, compressing fab capex across the programme. The downside case is familiar: fab slippage past 2028, design talent drain, and a fund that disburses slowly while competitors accelerate.
The asymmetry is clear: design firms and precision-equipment suppliers have the most to gain, while pure-play assembly and packaging operators without design IP are the most exposed to being squeezed in the middle. States that move quickly on land, power and clearances will capture the cluster effects; late movers will find the capital already committed elsewhere.
India's semiconductor bet is no longer just about building fabs — it is about owning the layers of the supply chain where the margins actually live. The money is now on the table; the next two years will show whether the ecosystem can pick it up.
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