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NextFin News - Taiwan Semiconductor Manufacturing Co. is considering a move into advanced memory chip production, specifically a next-generation architecture known as 3D DRAM, at the request of Nvidia Corp., its biggest customer, according to people familiar with the matter. The report sent TSMC's U.S.-listed shares up 7.7% on Friday, a sharp reversal after a 10.8% drop in the prior session, and it reframed a question the semiconductor industry has treated as settled for four decades: who is allowed to make memory.
The report, published on November 6, 2026, said TSMC has recently begun drafting plans to produce the chips. It is not a final decision, and the company has not confirmed the effort. But coming less than three weeks after reports that Samsung Electronics agreed to use TSMC's 3-nanometer process for the base die of Nvidia's next-generation custom memory, the episode points to something larger than one product line. The memory wall - the widening gap between how fast AI processors compute and how fast memory can feed them - is now pressing the industry's oldest boundary to collapse.
The Memory Wall Has Become the AI Supply Chain's Deciding Constraint
For most of 2026, the semiconductor shortage story has been told as a compute story: not enough GPUs, not enough advanced-node wafers, not enough packaging. The deeper truth is that the bottleneck has migrated downstream, into the memory that sits beside the GPU. TSMC's advanced packaging capacity, CoWoS, is projected to reach 120,000 to 140,000 wafers per month by the end of 2026, up from roughly 70,000 in 2025, with outsourced partners adding another 50,000 to 60,000. Even so, the industry still faces a shortfall of roughly 10%, narrowed from about 20% in late 2025, and lead times for CoWoS packaging run 52 to 78 weeks. Nvidia alone has reserved roughly 60% of TSMC's 2026 CoWoS output.
That is the mechanism behind the memory push. An AI accelerator is only as fast as the memory stacked next to it. High-bandwidth memory, or HBM, has become the critical enabler, and the base die - the logic layer at the bottom of the HBM stack that controls data read and write operations and error correction - is increasingly where performance is determined. As customers demand custom HBM with additional logic functions integrated into that base die, the value center of the memory stack is shifting from the DRAM capacitors toward the logic layer. That is TSMC's home turf.
The shift is already underway, and it is not theoretical. In mid-October, reports said Samsung accepted Nvidia's requirements to fabricate the base die of its next-generation NVHBM custom memory on TSMC's 3-nanometer process - a first for the two companies at this stage. Micron Technology has similarly tapped TSMC to make the base logic die for its HBM4E, targeting production in 2027. When the two largest memory makers hand their most advanced logic layer to the world's dominant foundry, the division of labor that has held since the 1980s - memory companies make memory, foundries make logic - is already breaking.
"Our business in the fourth quarter was supported by strong demand for our leading-edge process technologies," TSMC Chief Financial Officer Wendell Huang said in a statement after the company's third-quarter results. "Moving into first quarter 2026, we expect our business to be supported by continued strong demand for our leading-edge process technologies."
The financial backdrop makes the strategic option credible. TSMC reported third-quarter net income of NT$763.06 billion, up 68.7% year over year, with earnings per share of NT$29.43, beating the NT$746.3 billion estimate. Consolidated revenue was NT$1,494.24 billion, or US$46.72 billion, up 50.9% year over year and 17.6% sequentially, with gross margin of 66.4%. For the fourth quarter, the company guided revenue to US$52.3 billion to US$54.3 billion - a 14% sequential increase and a 58% year-over-year jump at the midpoint - and raised its full-year 2026 revenue growth outlook to around 44% in U.S. dollar terms. Chief Executive C.C. Wei has said he is "really jealous" of memory companies and their gross margins, which have run near 86% in the current cycle.
Why TSMC, and Why 3D DRAM Is the Right Door
The choice of 3D DRAM as the entry point is not accidental. Conventional DRAM scaling is running into physics: below roughly 16 nanometers, planar memory cells suffer from current leakage and signal interference, and shrinking further yields diminishing returns. 3D DRAM solves this by stacking memory cells vertically - using vertical channel transistors, vertical gate architectures, and through-silicon vias - a manufacturing challenge that looks far more like advanced logic packaging than like traditional memory fabrication. It relies on deposition, etching, and hybrid bonding, the exact toolset TSMC has been scaling for CoWoS and its SoIC 3D-stacking technology.
TSMC has already put DRAM-on-logic on its roadmap. At its 2026 Open Innovation Platform ecosystem forum, the company outlined a path toward DRAM integrated directly on logic, targeting roughly three times the bandwidth of HBM5E at under 1 picojoule per bit, with the technology appearing around 2029. That is a foundry speaking the language of memory - and it is a language the memory makers are also learning. SK Hynix demonstrated a five-layer 3D DRAM prototype in 2024 with a 56.1% yield; Samsung is developing vertical channel transistor DRAM; Micron holds more than 30 patents related to 3D DRAM as of August 2022, roughly two to three times the count of the two Korean vendors.
There is also a neutrality argument, and it may be the decisive one. TSMC's business model rests on not competing with its customers. The memory makers do not have that luxury: Samsung operates a foundry business that competes directly with TSMC, and SK Hynix and Micron are both customers and rivals in the AI accelerator ecosystem. Nvidia, which consumes the majority of advanced HBM, has an incentive to standardize the base die across three competing suppliers through a single neutral fabricator. A TSMC-made base die is the one component all three memory houses can accept without handing a competitor the keys to their product differentiation.
The economics reinforce the logic. Roughly 55% to 70% of 2026 revenue growth at the major memory makers has come from price increases, compared with 15% to 25% at TSMC and the Japanese equipment suppliers, according to industry analysis. Memory is a brutally cyclical commodity business where pricing power comes and goes with the supply cycle. TSMC's 66.4% gross margin in the third quarter reflects a different model: pricing power derived from technological leadership and capacity scarcity, not from commodity swings. For TSMC, memory is not a bet on DRAM prices; it is a bet on owning the logic-adjacent layer of the stack where the margins live.
The capital math also favors the foundry. TSMC has held its 2026 capital budget at US$60 billion to US$64 billion while still funding the 2-nanometer ramp and overseas fabs - a scale of sustained investment that only a handful of companies on earth can match. Building a memory business from scratch would require tens of billions more, and the payoff would arrive years after the spending. That is why the report's "mulling" framing matters: this is a strategic option being priced, not a capital program being executed.
The Strongest Case Against the Thesis
The counter-argument is substantial and should not be waved away. TSMC has zero track record of volume DRAM production. Memory is a capital-intensive, price-volatile commodity business that contradicts the very foundry-neutrality model that made TSMC the most valuable company in the semiconductor supply chain. And the timeline is long: realistic mass-production scenarios for 3D DRAM point to the 2032-2035 timeframe, not the current AI buildout. The report itself says TSMC is "mulling" the move and has "begun drafting plans" - language that describes a study, not an approved capital program. A paper plan drafted at a customer's request is not a revenue line.
There is force to this view. The memory makers are not passive. Samsung has allocated more than half of its current 4-nanometer capacity to HBM4 base-die production and is moving its custom HBM logic to a 2-nanometer node. SK Hynix, which held 50% of global HBM revenue in the second quarter of 2026, ahead of Samsung at 33% and Micron at 18%, built that lead on early qualification of HBM3E with Nvidia and has no intention of ceding the base die without a fight. The two Korean companies have already framed memory-logic integration as their own vision, presenting jointly with TSMC at a 2026 symposium on the topic.
The answer to the counter-thesis is that the near-term play is not 3D DRAM volume at all. It is the base-die foundry shift that is already happening: Samsung's NVHBM and Micron's HBM4E both route their most logic-intensive layer through TSMC. 3D DRAM is the strategic option that locks in that value capture for the next architecture. And neutrality is precisely why Nvidia wants TSMC in the role - Samsung cannot be the neutral arbiter for SK Hynix's and Micron's custom memory while competing with them in foundry and end products. The structural question is not whether TSMC will ship 3D DRAM in 2027; it is whether the base die becomes a standardized foundry product, and on that question the evidence from the past year points one way.
The falsifying signal is concrete. If TSMC does not confirm a memory partnership, release a 3D DRAM process design kit, or secure a second base-die customer beyond Nvidia by the end of 2027 - or if SK Hynix and Micron keep their HBM4E base-die production in-house through qualification - then the structural-shift thesis is wrong, and this is a long-dated research project rather than the redrawing of an industry boundary.
What Comes Next: Three Time Horizons
The forward picture splits cleanly by horizon, and the three horizons do not point in the same direction.
In the short term, through 2027, the story is sentiment and base-die orders, not memory revenue. TSMC's actual constraint remains 2-nanometer logic capacity and CoWoS packaging, not memory. The company's 2-nanometer ramp is already diluting gross margin, and its fourth-quarter guidance implies continued heavy investment. Any confirmed memory partnership would be multiple, but the revenue impact would be negligible against a US$46.7 billion quarterly run rate.
In the medium term, 2028 to 2030, DRAM-on-logic moves from roadmap to qualification. HBM5 and HBM5E cycles will test whether the base die has become a standardized, foundry-sourced component. This is where the second-order effect shows up: if the base die standardizes, memory vendors risk being reduced to suppliers of capacitor stacks - high-volume, yes, but with the intelligence and the margin migrating to the logic layer. That is the exact erosion TSMC has spent four decades avoiding in its own business.
In the long term, 2032 to 2035, 3D DRAM mass production is the regime-shift scenario. If TSMC arrives early with a manufacturable process, it adds a high-margin memory leg to an AI franchise that already spans logic, packaging, and now memory architecture. If the technology slips past 2035, or if the memory makers successfully defend in-house production, TSMC's memory effort stays a paper plan - and the industry boundary holds.
Three scenarios frame the outcome. The base case is that TSMC becomes the neutral base-die foundry for custom HBM while the memory makers retain the DRAM stack - a division that gives Nvidia standardization without disintermediating its suppliers. The upside case is that TSMC captures 3D DRAM early and adds a durable, high-margin memory business to its AI platform. The downside case is that the memory makers reject the foundry model, 3D DRAM slips indefinitely, and TSMC's drafting effort never becomes a fab.
For investors, the asymmetry runs through the supply chain rather than through a single stock. TSMC benefits in every scenario where the base die standardizes. Advanced packaging suppliers - ASE, SPIL, Amkor - benefit from the same memory-logic integration regardless of who makes the DRAM. Semiconductor equipment makers focused on deposition, etching, and hybrid bonding gain exposure to a new class of memory fab, a market that the DRAM industry will need to fund as it replaces planar scaling with vertical stacking. The memory makers are supported in the near term by HBM scarcity - demand has outpaced supply since 2023 and is expected to persist well into the decade - but face a structural question about where value accrues in the stack they helped create.
The memory wall did not just create a shortage. It redrew the map of who owns the high ground in AI hardware, and for the first time the foundry is standing on the memory side of the line. Whether TSMC stays there depends less on whether it can make DRAM than on whether the industry decides the smartest part of memory is no longer the memory at all.
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